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| MICRF500 Micrel MICRF500 700MHz to 1.1GHz RadioWireTM RF Transceiver Final General Description The MICRF500 is a single chip UHF transceiver designed for spread spectrum communication (FHSS) intended for ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands from 700MHz to 1100MHz with FSK data rates up to 128k baud. The transmitter consists of a PLL frequency synthesizer and a power amplifier. The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, dualmodulus prescaler, programmable frequency dividers and a phase-detector. The loop filter is external for flexibility and can be a simple passive circuit. The VCO is a Colpitts oscillator which requires an external resonator and varactor. FSK modulation can be applied externally to the VCO. The synthesizer has two different N, M and A frequency dividers. FSK modulation can also be implemented by switching between these dividers (max. 2400bps). The lengths of the N and M and A registers are 12, 10 and 6 bits respectively. For all types of FSK modulation, data is entered at the DATAIXO pin (see application circuit). The output power of the power amplifier can be programmed to eight levels. A lock detect circuit detects when the PLL is in lock. In receive mode the PLL synthesizer generates the local oscillator (LO) signal. The N, M and A values that give the LO frequency are stored in the N0, M0 and A0 registers. The receiver is a zero intermediate frequency (IF) type in order to make channel filtering possible with low-power integrated low-pass filters. The receiver consists of a low-noise amplifier (LNA) that drives a quadrature mixer pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel includes a preamplifier, a third order Sallen-Key RC low pass filter that protects the following gyrator filter from strong adjacent channel signals and finally, a limiter. The main channel filter is a gyrator capacitor implementation of a seven-pole elliptic low pass filter. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the Sallen-Key RC filter can be programmed to four different frequencies: 10kHz, 30kHz, 60kHz and 200kHz. An external resistor adjusts the cut-off frequency of the gyrator filter. The demodulator demodulates the I and Q channel outputs and produces a digital data output. It detects the relative phase of the I and the Q channel signal. If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data `1'). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data `0'). The output of the receiver is available on the DATAIXO pin. A RSSI (Receive Signal Strength Indicator) circuit indicates the received signal level. RadioWireTM A two pin serial interface is used to program the circuit. External components are necessary for RF input and output impedance matching and decoupling of power. Other external components are the VCO resonator circuit with varactor, crystal, feedback capacitors and components for FSK modulation with the VCO, loop filter, bias resistors for the power amplifier and gyrator filters. A T/R switch can be implemented with 2-pin diodes. This gives maximum input sensitivity and transmit output power. Features * * * * * Frequency range: 700MHz to 1100MHz Modulation: FSK RF output power: 10dBm Sensitivity (19.2k bauds, BER=10-3): -104dBm Maximum data rate: 128k bauds Applications * * * * * * * Telemetry Remote metering Wireless controller Wireless data repeaters Remote control systems Wireless modem Wireless security system Ordering Information Part Number MICRF500BLQ Ambient Temp. Range -40C to +85C Package 44-Lead LQFP RadioWire is a trademark of Micrel, Inc. Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com March 2003 1 MICRF500 MICRF500 Micrel Pin Configuration VB_IP QCHC ICHC IFQINN IFQINP MIXQOUTN MIXQOUTP IFIINN IFIINP MIXIOUTN MIXIOUTP IFGND IFVDD ICHOUT QCHOUT OSCVDD OSCIN OSCGND GND CMPOUT CMPR MOD 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 MIXERVDD MIXERGND LNA_C RFGND2 RFIN RFVDD RFGND RFOUT PABIAS PA_C DIGGND Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin Name IFGND IFVDD ICHOUT QCHOUT OSCVDD OSCIN OSCGND GND CMPOUT CMPR MOD XOSCIN XOSCOUT LD_C LOCKDET RSSI PDEXT DATAC DATAIXO CLKIN REGIN DIGVDD DIGGND Pin Function IF Ground IF Power I-Channel Output Q-Channel Output Colpitts Oscillator Power Colpitts Oscillator Input Colpitts Oscillator and Substrate Ground Substrate Ground Charge Pump Output Charge Pump Resistor Input Output for VCO Modulation Crystal Oscillator Input Crystal Oscillator Output External Capacitor for Lock Detector Lock Detector Output Received Signal Strength Indicator Output Power Down Input (0=Power Down) Data Filter Capacitor Data Input/Output Clock Input for Programming Data Input for Programming Digital Circuitry Power Digital Circuitry Ground MICRF500 XOSCIN XOSCOUT LD_C LOCKDET RSSI PDEXT DATAC DATAIXO CLKIN REGIN DIGVDD 44-Pin LQFP (BLQ) 2 March 2003 MICRF500 Micrel Pin Description, cont't Pin Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name PA_C PABIAS RFOUT RFGND RFVDD RFIN RFGND2 LNA_C MIXERGND MIXERVDD MIXIOUTP MIXIOUTN IFIINP IFIINN MIXQOUTP MIXQOUTN IFQINP IFQINN ICHC QCHC VB_IP Pin Function Capacitor for Slow Ramp Up/Down of PA External Bias Resistor for Power Amplifier Power Amplifier Output LNA, PA and Substrate Ground LNA and PA Power Low Noise RF Amplifier (LNA) Input LNA First Stage Ground External LNA Stabilizing Capacitor Mixer Ground Mixer Power I-Channel Mixer Positive Output I-Channel Mixer Negative Output I-Channel IF Amplifier Positive Input I-Channel IF Amplifier Negative Input Q-Channel Mixer Positive Output Q-Channel Mixer Negative Output Q-Channel IF Amplifier Positive Input Q-Channel IF Amplifier Negative Input I-Channel Amplifier Capacitor Q-Channel Amplifier Capacitor Gyrator Filter Resistor March 2003 3 MICRF500 MICRF500 Micrel Absolute Maximum Ratings (Note 1) Maximum Supply Voltage (VDD) ................................... +7V Maximum NPN Reverse Base-Emitter Voltage .......... +2.5V Storage Temperature Range (TS) ............ -55C to +150C ESD Rating, Note 3 .................................................... 500V Operating Ratings (Note 2) Supply Voltage (VIN) ................................... +2.5V to +3.4V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP(JA)-Multilayer board ............................. 46.3C/W Electrical Characteristics FREF = 850MHz, VDD = 2.5 to 3.4V, TA = 25C, unless otherwise specified. Parameter Overall Operating Frequency Power Down Current Logic High Input, VIH Logic Low Input, VIL DATAIXO, Logic High Output (VOH) DATAIXO, Logic Low Output (VOL) LockDet, Logic High Output (VOH) LockDet, Logic Low Output (VOL) Clock/Data Frequency Clock/Data Duty-Cycle Data Setup to Clock (rising edge) VCO and PLL Section Prescaler Divide Ratio Reference Frequency PLL Lock Time (int. modulation) PLL Lock Time (ext. modulation) Rx - (Tx with PA on) Switch Time Charge Pump Current Transmit Section Output Power Transmit Data Rate (ext. modulation) Note 4 Transmit Data Rate (int. modulation) Note 5 Frequency Deviation to Modulation Rate Ratio Current Consumption Transmit Mode unfiltered FSK 10 dBm, RLOAD = 50 1.0 1.5 50 mA fOUT = 850MHz RLOAD = 50, VDD = 3.0V 10 19.2 128 2.4 dBm kbauds kbauds 4kHz loop filter bandwidth 1kHz loop filter bandwidth 1kHz loop filter bandwidth 1 4 2.5 95/380 125/500 155/620 64/65 40 MHz ms ms ms A 25 25 IOH = -500A IOL = 500A IOH = -100A IOL = 100A VDD-0.25 0.25 10 75 VDD-0.3 0.3 70% 30% 700 850 <1 1100 2 MHz A VDD VDD V V V V MHz % ns Condition Min Typ Max Units MICRF500 4 March 2003 MICRF500 Parameter Receive Section Receiver Sensitivity (Note 6) Input 1dB Compression Level Input IP3 Input Impedance RSSI Dynamic Range RSSI Output Voltage Adjacent Channel Rejection: fC = 10kHz fC = 30kHz fC = 60kHz fC = 200kHz Blocking Immunity (1MHz) PIN = -100dBm PIN = -30dBm 25kHz channel spacing 100kHz channel spacing 200kHz channel spacing 700kHz channel spacing RC filter: RC filter: RC filter: RC filter: fC = 10kHz fC = 30kHz fC = 60kHz fC = 200kHz Condition fIN = 850MHz BER=10-3 -1046 -34 -24 22.5-j28.5 60 0.7 2.1 26 37 45 48 66 61 59 53 175 1 gyrator filter fC = 60kHz 12 300 Min Typ Max Micrel Units dBm dBm dBm W dB V V dB dB dB dB dB dB dB kHz ms mA A Maximum Receiver Bandwidth Receiver Settling Time Current Consumption Receive Mode Current Consumption XCO Note 1. Note 2. Note 3. Note 4. Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Modulation is applied to the VCO and therefore the modulation cannot have any DC component. Some kind of coding is needed to ensure that the modulation is DC free, e.g., Manchester code or block code. With Manchester code the bitrate is half the baudrate, but with 3B4B block code the bitrate is 3/4 of the baudrate. Bitrate is the same as the baudrate. Measured at 19.2k bauds and frequency deviation 25kHz (external modulation), jitter of received data: < 45%. Note 5: Note 6: Output Power vs. Current @ 25C 15 10 POUT (dBm) 5 0 -5 -10 10 15 20 25 30 35 40 45 50 ITOT (mA) March 2003 5 MICRF500 MICRF500 Micrel Functional Diagram 33 32 31 30 29 28 27 26 25 24 23 34 LNA PA 22 35 90 36 Prescaler 64/65 C o n t r Logic o l Control 21 20 37 A1/A0 38 A-counter 39 RC Filters Gyrator Filters R S S I N1/N0 N-counter I n t e r f a c e 19 18 17 40 16 41 M-counter M1/M0 15 42 LD 43 VCO Demod 44 1 2 3 4 5 6 7 8 Phase Detector 14 13 Charge Pump XCO 12 9 10 11 Figure 1. Transceiver Internal Blocks MICRF500 6 March 2003 MICRF500 Micrel The varactor SMV1215-011 is a single variable capacitance diode manufactured by Skyworks Solutions (formerly Alpha Industries). The pin diode SMP1320 is also manufactured by Skyworks Solutions. Typical Application Figure 2 shows an example of a transceiver with modulation applied to the VCO. The VCO and matching components are optimized for 915MHz, 120kbps data rate. The inductors and trimming capacitors must have a good high frequency performance. C7 4.7n C8 4.7n C9 1n C10 1n C11 1n C12 1n VDD R5 62 C5 47p MIXER VDD MIXER GND LNA_C RFGND2 RFIN 33 VDD R4 10 R6 1k 44 43 42 41 40 39 38 37 36 35 34 VB_IP QCHC ICHC IFQINN IFQINP MIXQOUTN MIXQOUTP IFIINN IFIINP MIXIOUTN MIXIOUTP VDD R1 30 1 IFGND IFVDD ICHOUT QCHOUT OSCVDD OSCIN OSCGND GND CMPOUT C30 47p C1 47p R2 0 IchOut QchOut R7 20k C38 L1 12n D1 SMV1215 R8 39k R13 270k C16 39n R10 16k C15 3.3n R11 100k R9 16k C13 4.7p 2 32 C26 10n 31 30 3 4 L2 5.1n ant-switch D2 SMP1320-079 C37 4p ANT VDD C28 18p C29 100p R14 2.2k C25 470p C35 47p C31 4.7p L5 10n R16 2.2k VDD C6 47p VDD L4 5.6n C4 47p 5 29 6 MICRF500 44-pin LQFP RFVDD RFGND RFOUT PABIAS PA_C 28 L3 8.7n 7 8 27 26 C36 1.5p C33 47p D3 SMP1320-079 9 25 CMPR 10 24 MOD 11 DIGGND 23 XOSCOUT LOCKDET C19 470p C32 6.8p DIGVDD DATAIX0 C34 10n C18 100n C17 68p 12 C22 7p C21 100p XOSCIN PDEXT REGIN DATAC CLKIN LD_C RSSI 13 14 15 16 17 18 19 20 21 22 C23 1n R3 39 Lock Det C20 4p to 10p PDEXT DATAIX0 CLKIN REGIN VDD R12 6.8k 10MHz C24 1n RSSI Figure 2. Application Circuit - Optimized for 915MHz. 120kbps March 2003 7 MICRF500 MICRF500 List of components Component R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R16 C1 C4 C5 C6 C7 Values 30 0 39 10 62 1k 20k 39k 16k 16k 100k 6.8k 270k 2.2k 2.2k 47pF 47pF 47pF 47pF 4.7nF Component C8 C9 C10 C11 C12 C13 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C28 C29 Values 4.7nF 1nF 1nF 1nF 1nF 4.7pF 3.3nF 39nF 68pF 100nF 470pF 4pF-100pF 100pF 7pF 1nF 1nF 470pF 10nF 18pF 100pF Component C30 C31 C32 C33 C34 C35 C36 C37 C38 L1 L2 L3 L4 L5 D1 D2 D3 crystal Values 47pF 5.6pF 6.8pF 47pF 10F 47pF 1.5pF 4pF (np) 12nH 5.1nH 8.7nH 5.6nH 10nH Micrel SMV1215-011 SMP1320-079 SMP1320-079 10MHz MICRF500 8 March 2003 MICRF500 Micrel DIFVDD Applications Information VCO and PLL Section The frequency synthesizer consists of a VCO, crystal oscillator, dual-modulus prescaler, programmable frequency dividers, phase-detector, charge pump, lock detector and an external loop filter. The dual-modulus prescaler divides the VCO-frequency by 64/65. This mode is controlled by the Adivider. There are two sets of M, N and A-frequency dividers. Using both sets in transmit mode, FSK can be implemented by switching between those two sets. The phase-detector is a frequency/phase detector with back slash pulses to minimize phase noise. The VCO, crystal oscillator, charge pump, lock detector and the loop filter will be described in detail below. Voltage Controlled Oscillator (VCO) VDD Pin 5 R7 20k loopfilter_output R8 39k C38 D1 SMV1215 Pin 7 L1 12nH C13 4.7p OSCOUT Pin 6 C36 1n C22 5.6p Pin 12 C20 2-6p 10MHz Pin 13 C21 47p DIGGND XOSCOUT Figure 4. Crystal Oscillator The crystal oscillator is tuned by varying the trimming capacitor C20. The drift of the RF frequency is the same as the drift of crystal frequency when measured in ppm. The total difference in ppm, f(ppm), between the tuned RF frequency and the drifted frequency is given by: f(ppm) = ST x T + n x t where: * ST is the total temperature coefficient of the oscillator frequency (due to crystal and components) in ppmC. * T is the change in temperature from room temperature, at which the crystal was tuned. * n is the ageing in ppm/year. * t is the time (in years) elapsed since the transceiver was last tuned. The demodulator will not be able to decode data when f(Hz) = f(ppm) x fRF is larger than the FSK frequency deviation. For small frequency deviations, the crystal should be pre-aged, and should have a small temperature coefficient. The circuit has been tested with a 10MHz crystal, but other crystal frequencies can be used as well. Prestart of XCO Figure 3. VCO The circuit schematic of the VCO with external components is shown in Figure 3. The VCO is basically a Colpitts oscillator. The oscillator has an external resonator and varactor. The resonator consists of inductor L1 and the series connection of capacitor C13, the internal capacitance and the capacitance of the varactor. The capacitance of the varactor (D1) decreases as the input voltage increases. The VCO frequency will therefore increase as the input voltage increases. The VCO has a positive gain (MHz/Volt). If necessary a parallel capacitor can be added next to D1 to bring the VCO tuning voltage to its middle range or VDD/2, which is measured at Pin 9 - CMPOUT. If the value of capacitor C13 becomes too small the amplitude of the VCO signal decreases, which leads to lower output power. The layout of the VCO is very critical. The external components should be placed as close to the input pin (Pin 6) as possible. The anode of D1 must be placed next to Pins 7 and 8 in the PCB layout. Ground vias should be next to component pads. Crystal Oscillator The crystal oscillator is the reference for the RF output frequency as well as for the LO frequency in the receiver. The crystal oscillator is a very critical block since very good phase and frequency stability is required. The schematic of the crystal oscillator with external components for 10MHz is shown in Figure 4. These components are optimized for a crystal with 15pF load capacitance. The start-up time of a crystal oscillator is typically some milliseconds. Therefore, to save current consumption, the MICRF500 circuit has been designed so that the XCO is turned on before any other circuit block. During start-up the XCO amplitude will eventually reach a sufficient level to trigger the M-counter. After counting two M-counter output pulses the rest of the circuit will be turned on. The current consumption during the prestart period is approximately 300A. Lock Detector The MICRF500 circuit has a lock detector feature that indicates whether the PLL is in lock or not. A logic high on Pin 15 (LOCKDET) means that the PLL is in lock. The phase detector output is converted into a voltage that is filtered by the external capacitor C23, connected to Pin 14, LDC. The resulting DC voltage is compared to a reference window set by bits Ref0 - Ref5. The reference window can be stepped up/down linearly between 0V, Ref0 - Ref5 = 1, and Ref0 - Ref5 = 0, which gives the highest value (DC voltage) of the reference window. The size of the window can either be equal to two (Ref6 = 1) reference steps or four reference steps (Ref6 = 0). March 2003 9 MICRF500 MICRF500 The bit setting that corresponds to lock can vary, depending on temperature, loop filter and type of varactor. Therefore, the lock detect circuit needs to be calibrated regularly by a software routine that finds the correct bit setting, by running through all combinations of bits Ref0 - Ref5. Depending on the size of the reference window, there will be several bit combinations that show lock. For instance, with a large reference window, as much as five bit combinations can make the lock detector show lock. To have the maximum robustness to noise, the third of the bit settings should be chosen. Charge Pump The charge pump can be programmed to four different modes with two currents, 125A and 500A. Bit 70 and 71 in the control word (cpmp1 and cpmp0) controls the operation. The four modes are: 1. cpmp1 = 0 Current is constant 125A. Used in cpmp0 = 0 applications where short PLL lock time is not important. 2. cpmp1 = 0 Current is constant 500A. Used in cpmp0 = 1 applications where a short PLL lock time is important, e.g., internal modulation. See "Modulation Inside PLL" section. 3. cpmp1 = 1 Current is 500A when PLL is out of cpmp0 = 0 lock and 125A when it is in lock. Controlled by LOCKDET (Pin 15). Lock time is halved. See "Modulation Outside PLL" section. 4. cpmp1 = 1 Same as above in Tx. In Rx the current cpmp0 = 1 is 500A. Used when using dual-loop filters. See "Modulation Outside PLL Dual-Loop Filters" section. Tuning of VCO and XCO There are two circuit blocks that may need tuning, the VCO and the crystal oscillator. VCO Tuning Micrel FSK Modulation The circuit has two sets of frequency dividers A0, N0, M0 and A1, N1, M1. The frequency dividers are programmed via the control word. A0, N0, M0 are to be programmed with the receive frequency and are used in receive mode. There are three ways of implementing FSK: * FSK modulation can be applied to the VCO. This way of implementing FSK modulation is explained more in detail in the next section. The values corresponding to the transmit frequency should be programmed in dividers A1, N1 and M1. Pin DATAIXO must be kept in tri-state from the time Tx-mode is entered until one starts sending data. * FSK modulation by switching between the two sets of A, N and M dividers. A, N and M values corresponding to the receive frequency and both transmit frequencies have to be found. In transmit the values corresponding to data `0' should be programmed in dividers A0, N0 and M0, and the values corresponding to data `1' should be programmed in dividers A1, N1 and M1. * FSK modulation by adding/subtracting 1 to divider A1. The frequency deviation will be equal to the comparison frequency. The values corresponding to the transmit frequency should be programmed in dividers A1, N1 and M1. For all types of FSK modulation, data is entered at the DATAIXO pin. Loop Filter The design of the loop filter is of great importance for optimizing parameters like modulation rate, PLL lock time, bandwidth and phase noise. Low bitrates will allow modulation inside the PLL, which means the loop will lock on different frequency for 1s and 0s. This can be implemented by switching the internal dividers (M, N and A). Higher modulation rates (above 2400bps) imply implementation of modulation outside the PLL. This can be implemented by applying the modulation directly to the VCO. Loop filter values can be found using an appropriate software program. Modulation Inside PLL When the VCO voltage is not at its mid-point, a capacitor may be added in parallel with D1or by small increments changes in the L1 or C13 values. This is particularly important when using VCO modulation. The gain curve of the VCO (MHz/Volt) is not linear and the gain will therefore vary with loop voltage. This means that the FSK frequency deviation also varies with loop voltage. When using internal modulation, tuning the VCO can be omitted as long as the VCO gain is large enough to allow the PLL to handle variations in process parameters and temperature without going out of lock. XCO Tuning Tune the trimming capacitor in the crystal oscillator to the precise desired transmit frequency. It is not possible to tune the crystal oscillator over a large frequency range. N, M and A values must therefore be chosen to give a RF frequency very close to the desired frequency. Because of the small tuning range the VCO will not go out of lock when tuning the crystal oscillator. MICRF500 10 A fast PLL requires a loop filter with relatively high bandwidth. If a second order loop filter is chosen, it may not give adequate attenuation of the comparison frequency. Therefore in the following example a third order loop filter is chosen. Example 1: 868MHz Radio frequency fRF Comparison frequency fC 100kHz Loop bandwidth BW 3.8kHz VCO gain Ko 30MHz/V Phase comparator gain Kd 500A/rad Phase margin j 62 Breakthrough suppression A 20dB March 2003 MICRF500 The component values will be: IN R101 C116 22n C115 1n R109 10k C101 100p 33k OUT Micrel through the Mod pin (Pin 11) which is a current output. The pin sources a current of 50A when Logic 1 is entered at the DATAIXO and drains the current for Logic 0. The capacitance of C17 will set the order of filtering of the baseband signal. A large capacitance will give a slow ramp-up and therefore a high order of filtering of the baseband signal, while a small capacitance gives a fast ramp-up, which in turn also gives a broader frequency spectrum. Resistors R11 and R12 set the frequency deviation. If C18 is large compared to C17, the frequency deviation will be large. R13 should be large to avoid influencing the loop filter. Pin DATAIXO must be kept in tri-state from the time Tx-mode is entered until one starts sending data. Modulation Outside PLL, Dual-Loop Filters Figure 5. Third Order Loop Filter With this loop filter, internal modulation up to 2400bps is possible. The PLL lock time from power-down to Rx will be approximately 1ms. Modulation Outside PLL (Closed Loop) When modulation is applied outside the PLL, it means that the PLL should not track the changes in the loop due to the modulation signal. A loop filter with relatively low bandwidth is therefore necessary. The exact bandwidth will depend on the actual modulation rate. Because the loop bandwidth will be significantly lower than the comparison frequency, a second order loop filter will normally give adequate attenuation of the comparison frequency. If not, a third order loop filter may give the extra attenuation needed. Example 2: 868MHz Radio frequency fRF Comparison frequency fC 140kHz Loop bandwidth BW 900Hz VCO gain Ko 30MHz/V Phase comparator gain Kd 125A/rad Phase margin j 61 The component values will be: IN C16 68n C15 4.7n R9 10k CmpR R10 10k OUT Modulation outside the PLL requires a loop filter with a relatively low bandwidth compared to the modulation rate. This results in a relatively long loop lock time. In applications where modulation is applied to the VCO, but at the same time a short start-up time from power down to receive mode is needed, dual-loop filters can be implemented. Figure 7 shows how to implement dual-loop filters. CMPOUT Pin9 C16 Pin10 FLC 68n R10 10k C15 4.7n C116 1n R109 10k C115 22n R102 33k C103 100p R8 89k towards_VCO R9 10k Pin4 DFC Figure 7. Dual-Loop Filters The loop filter used in transmit mode is made up of C15, C16, R9 and R10. The fast lock feature is also included (internal NMOS controlled by FLC, Fast Lock Control). This filter is automatically switched in/out by an internal NMOS at Pin 4, QchOut, which is controlled by DFC (Dual Filter Control). Bits OutS2, OutS1, OutS0 must be set to 110. When QchOut is used to switch the Tx loop filter to ground, neither QchOut nor IchOut can be used as test pins to look at the different receiver signals. The receive mode loop filter comprises C115, C116, R109, R101 and C101. Modulation Outside PLL (Open Loop) Figure 6. Second Order Loop Filter Data rates above approximately 19200baud (including Manchester coding) can be used with this loop filter without significant tracking of the modulating signal. PLL lock time will be approximately 4ms. If a faster PLL lock time is wanted, the charge pump can be made to deliver a current of 500A per unit phase error, while an open drain NMOS on chip (Pin 10, CmpR) switches in a second damping resistor (R10) to ground as shown in Figure 6. Once locked on the correct frequency, the PLL automatically returns to standard low noise operation (charge pump current: 125A/rad). If correct settings have been made in the control word (cpmp1 = 1, cpmp0 = 0), the fast locking feature is activated and will reduce PLL lock time by a factor of two without affecting the phase margin in the loop. Components C17, C18 C19, R11, R12 and R13 (see application circuit) are necessary if FSK modulation is applied to the VCO. Data entered at the DATAIXO pin will then be fed March 2003 11 In this mode the charge pump output is tri-stated. The loop is open and will therefore not track the modulation. This means that the loop filter can have a relatively high bandwidth, which give short switching times. However, the loop voltage will decrease with time due to current leakage. The transmit time will therefore be limited and is dependent on the bandwidth of the loop filter. High bandwidth gives low capacitor values and the loop voltage will decrease faster, which gives a shorter transmit time. The loop is closed until the PLL is locked on the desired frequency and the power amplifier is turned on. The loop immediately opens when the modulation starts. The loop will not track the modulation, but the modulation still needs to be DC free due to the AC coupling in the modulation network. MICRF500 MICRF500 Micrel Transmit Power Amplifier (PA) The power amplifier is biased in class AB. The last stage has an open collector, and an external load inductor (L2) is therefore necessary. The DC current in the amplifier is adjusted with an external bias resistor (R14). A good starting point when designing the PA is a 1.5k bias resistor which gives a bias current of approximately 50A. This will give a bias current in the last stage of about 15mA. The impedance matching circuit will depend on the type of antenna used, but should be designed for maximum output power. For maximum output power the load seen by the PA must be resistive and should be about 100. The output power is programmable in eight steps, with approximately 3dB between each step. This is controlled by bits Pa2 - Pa0. To prevent spurious components from being transmitted the PA should be switched on/off slowly, by allowing the bias current to ramp up/down at a rate determined by the external capacitor C25 connected to Pin 24. The ramp up/down current is typically 1.1A, which makes the on/off rate for a 3.0V power supply 2.6s/pF. Turning the PA on/off affects the PLL. Therefore the on/off rate must be adjusted to the PLL bandwidth. PA Buffer A buffer amplifier is connected between the VCO and the PA to ensure that the input signal of the PA has sufficient amplitude to achieve the desired output power. This buffer can be bypassed by setting the bit Gc to 0. Figure 8. Input Impedance Sallen-Key Filter and Preamplifier Each channel includes a preamplifier and a prefilter, which is a three-pole elliptic Sallen-Key low pass filter with 20dB stopband attenuation. It protects the following gyrator filter from strong adjacent channel signals. The preamplifier has a gain of 20dB when bit Gc = 0 and 30dB when bit Gc = 1. The output voltage swing is about 200mVPP for the 30dB gain setting and 1VPP for the 20dB gain setting. The third order Sallen-Key low pass filter is programmable to four different cut-off frequencies according to the table below: Fc1 0 0 1 1 Fc0 0 1 0 1 Cut-Off Frequency (kHz) 10 2.5 30 7.5 60 15 200 50 Recommended Channel Spacing 25kHz 100kHz 200kHz 700kHz Receive Front End (LNA and Mixers) A low noise amplifier in RF receivers is used to boost the incoming signal prior to the frequency conversion process. This is important in order to prevent mixer noise from dominating the overall front end noise performance. The LNA is a two-stage amplifier and has a nominal gain of 23dB at 900MHz. The LNA has a dc feedback loop, which provides bias for the LNA. The external capacitor C26 decouples and stabilizes the overall dc feedback loop, which has a large low frequency loop gain. Figure 8 shows the input impedance of the LNA. Input matching is very important to get high receive sensitivity. The LNA can be bypassed by setting bit ByLNA to `1'. This is useful for very strong signal levels. The RSSI signal can be used to drive a microcontroller in a way when a strong RF income signal is present the LNA can be bypassed. This will increase the dynamic range by approximately 25dB. The mixers have a gain of about 12dB at 900MHz. The differential outputs of the mixers are available at Pins 34, 35 and at Pins 38, 39. The output impedance of each mixer is about 15k. For the 10kHz cut-off frequency the first pole must be generated externally by connecting a 820pF capacitor between the outputs of each mixer. For the 30kHz cut-off frequency a 68pF capacitor is needed between the outputs. As the cut-off frequency of the gyrator filter can be set by varying an external resistor, the optimum channel spacing will depend on the cut-off frequencies of the Sallen-Key filter. The table above shows the recommended channel spacing depending on the different bit settings. Gyrator Filter The main channel filter is a gyrator capacitor implementation of a seven-pole elliptic low pass filter. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. An external resistor can adjust the cutoff frequency of the gyrator filter. The following table shows how the cut-off frequency varies with bias resistor: MICRF500 12 March 2003 MICRF500 Bias Resistor (k) 2.2 6.8 8.2 15 30 47 Cut-Off Frequency (kHz) 175 70 55 30 14 8 Micrel Limiter The limiter serves as a zero crossing detector, thus removing amplitude variations in the IF signal, while retaining only the phase variations. The limiter outputs are ideally suited to measure the I-Q phase difference, since its outputs are square waves with sharp edges. Demodulator The demodulator demodulates the I and Q channel outputs and produces a digital data output. It detects the relative phase difference between the I and the Q channel signals. For every edge (positive and negative) of the I channel limiter output, the amplitude of the Q channel limiter output is sampled, and vice versa. The output of the demodulator is available on the DATAIXO pin. The data output is therefore updated 4 times per cycle of the IF signal. This also means that the maximum jitter of the data output is 1/(4xf) (valid only for zero frequency offsets). If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data `1'). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data `0'). The inputs and the output of the demodulator are filtered by first order RC low pass filters and then amplified by Schmitt triggers to produce clean square waves. It is recommended for low bitrates (<10kbps) that an additional capacitor is connected to Pin 18 (DataC) to decrease the bandwidth of the Rx data signal filter. The bandwidth of the filter must be adjusted for the bitrate. This functionality is controlled by bit RxFilt. Received Signal Strength Indicator (RSSI) The RSSI provides a DC output voltage proportional to the strength of the RF input signal. A graph of a typical RSSI response is shown in Figure 9 (fDEV = 30kHz, Gc=1). 2.2 2 1.8 The gyrator filter cut-off frequency should be chosen to be approximately the same as the cut-off frequency of the Sallen-Key filter. The maximum cut-off frequency of the gyrator filter is 175kHz. Cut-Off Frequency Setting The cut-off frequency must be high enough to pass the received signal (frequency deviation + modulation). The minimum cut-off frequency is given by: fC(min) = fDEV + Baudrate/2 For a frequency deviation of fDEV = 30kHz and a baudrate of 20k baud, the minimum cut-off frequency is 40kHz. Bit setting Fc1 = 1 and Fc0 = 0, which gives a cut-off of (60 15) kHz, would be the best choice. The gyrator filter bias resistor should therefore be 7.5k or 8.2 k, to set the gyrator filter cut-off frequency to approximately 60kHz. The crystal tolerance must also be taken into account when selecting the receiver bandwidth. If the crystal has a temperature tolerance of say 10ppm over the total temperature range, the incoming RF signal and the LO signal can theoretically be 20ppm away from each other. The frequency deviation must always be larger than the maximum frequency drift for the demodulator to be able to demodulate the signal. The minimum frequency deviation (fDEVmin) is equal to the baudrate, according to the specification on page 2. This means that the frequency deviation has to be at least equal to the baudrate plus the maximum frequency drift. The frequency deviation may therefore vary from the minimum frequency deviation to the minimum frequency deviation plus two times the maximum frequency drift. The minimum cut-off frequency when crystal tolerances are considered is therefore given by: fCmin = f x 2 fDEVmin + Baudrate/2 where f is the maximum frequency drift between the LO signal and the incoming RF signal due to crystal tolerances. A frequency drift of 20ppm is 8680Hz at 434MHz. The frequency deviation must be higher than 28.68kHz for a baudrate of 20k baud. The frequency deviation may then vary from 20kHz, when the RF signal is 20ppm lower than the LO signal; to 37.36kHz when the RF signal is 20ppm higher than the LO signal. The minimum cut-off frequency is tueref*re 47.36kHz. VOUT (V) 1.6 1.4 1.2 1 0.8 -90 -80 -70 -60 -50 -40 -30 -110 -100 PIN (dBm) Figure 9. Typical RSSI Characteristics This graph shows a range of 0.7V to 2.05V over a RF input range of 70dB. The RSSI can be used as a signal presence indicator. When a RF signal is received, the RSSI output increases. This could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life. Another application for which the RSSI could be used is to determine if transmit power can be reduced in a system. If the RSSI detects a strong signal, it could tell the transmitter to reduce the transmit power to reduce current consumption. March 2003 13 -20 0.6 MICRF500 MICRF500 Micrel Programming A two-line bus is used to program the circuit; the two lines being CLKIN and REGIN. The 2-line serial bus interface allows control over the frequency dividers and the selective powering up of Tx, Rx and Synthesizer circuit blocks. The interface consists of an 80-bit programming register. Data is entered on the REGIN line with the most significant bit first. The first bit entered is called p1, the last one p80. The bits in the programming register are arranged as shown in Table 1. p1 - p6 A1 p59 Pa1 p67 Ref2 p75 OutS1 p7 - p12 A0 p60 Pa0 p68 Ref1 p76 OutS0 p13 - p24 N1 p61 Gc p69 Ref0 p77 Mod1 p25 - p36 N0 p62 ByLNA p70 Cpmp1 p78 Mod0 p37 - p46 M1 p63 Ref6 p71 Cpmp0 p79 RT p47 - p56 M0 p64 Ref5 p72 Fc1 p80 Pu p57 RxFilt p65 Ref4 p73 Fc0 -- -- p58 Pa2 p66 Ref3 p74 OutS2 -- -- Table 1. Bit Allocation MICRF500 14 March 2003 MICRF500 Name A1 A0 N1 N0 M1 M0 RxFilt Pa2 Pa1 Pa0 Gc ByLNA Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Cpmp1 Cpmp0 charge pump setting: Cpmp1=0, Cpmp0=0 : 125A Cpmp1=0, Cpmp0=1 : 500A Cpmp1=1, Cpmp0=0 : controlled by LockDet (LD) LD=0: 500A, LD=1: 125A Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is 500A. Active RC-filter settings Fc1=0, Fc0=0 : 10kHz Fc1=0, Fc0=1 : 30kHz I- and Q-channel output select OutS2 OutS1 0 0 Fc1=1, Fc0=0 : 60kHz Fc1=1, Fc0=1 : 200kHz QchOut high Z OutS2 1 OutS1 0 OutS0 0 IchOut lim_qch all 0's: highest reference all 1's: lowest reference reference settings in lock detector Description frequency divider A1, 6 bits frequency divider A0, 6 bits frequency divider N1, 12 bits frequency divider N0, 12 bits frequency divider M1, 10 bits frequency divider M0, 10 bits 1=external capacitor for filtering of Rx data signal gain setting in power amplifier pa2, pa1, pa0 = 0 : lowest output power pa2, pa1, pa0 = 1 : highest output power gain control in power amplifier buffer: 1=high gain gain control in preamplifier in receiver: 1=high gain 1 = the LNA is bypassed Micrel Fc1 Fc0 OutS2 OutS1 OutS0 OutS0 IchOut 0 high Z QchOut gm_qch lim_ich Dual LF M_div 0 0 1 sk_ich sk_qch 1 0 1 gm_ich 0 1 0 gm_ich gm_qch 1 1 0 high Z 0 1 1 lim_ich lim_qch 1 1 1 N_div sk:_*:Sallen-Key filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output (for testing). 110 is for dual-loop filter applications, see "Modulation Outside PLL, Dual-Loop Filters." Mod1 = 0, Mod0 = 0: FSK modulation can be applied to the VCO Mod1 = 0, Mod0 = 1: FSK modulation can be applied to the VCO: open loop modulation Mod1 = 1, Mod0 = 0: FSK modulation by switching between the two sets of dividers Mod1 = 1, Mod0 = 1: FSK modulation by adding/subtracting 1 to divider A1: fdeviation = fcomparison 0 = receive mode 1 = transmit mode 1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt) Mod1 Mod0 RT Pu Table 2. Bit Description March 2003 15 MICRF500 MICRF500 When FSK modulation is applied to the VCO the PLL is using the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0 it is possible to switch between the different dividers in the PLL. DATAIXO controls the switching. When DATAIXO = 0 the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the PLL uses dividers A1, N1 and M1. Switching between the different dividers can be used to implement FSK modulation. The N, M and A values can be calculated from the formula: f fRF fC = XCO = M 64 x N + A where fC is the comparison frequency. Micrel 6. A new control word is entered into the first register. A transition on the REGIN signal when CLKIN is high will now turn the power amplifier off. 7. When the power amplifier is turned off an internal load pulse is generated. The new control word is loaded into the parallel register and the circuit enters a new mode (in this case power down mode). CLKIN must go low after the internal load pulse is generated. As long as transitions on REGIN are avoided when CLKIN is high, a new control word can be clocked into the first register any time without affecting the operation of the transceiver. Example 1. fRF = 869.0MHz, frequency deviation: 10kHz, fXCO = 10.00MHz. FSK modulation is implemented by switching between dividers. A1 Tx Rx 9 50 RxFilt A0 27 50 Pa2 1 1 Ref5 0 0 N1 137 135 Pa1 1 1 Ref4 0 0 N0 134 135 Pa0 1 1 Ref3 0 0 Fc1 0 0 Mod0 0 0 M1 101 100 Gc 1 1 Ref2 0 0 Fc0 1 1 RT 1 0 M0 99 100 ByLNA 0 0 Ref1 0 0 OutS2 0 0 Pu 1 1 The 80bit control word is first read into a shift-register, and is then loaded into a parallel register by a transition of the REGIN signal (positive or negative) when the CLKIN signal is high. The circuit then goes directly into the specified mode (receive, transmit, etc.). 1 CLKIN REGIN LOAD_INT PA_C LOCKDET 23 4 5 6 7 Tx Rx 0 0 Ref6 Tx Rx 0 0 Ref0 Cpmp1 Cpmp0 1 1 OutS0 0 0 0 0 Mod1 1 1 Tx Rx 0 0 OutS1 Figure 10. Timing of CLKIN, REGIN and the Internal LOAD_INT and PA_C Signals 1. The second last bit is clocked into the first shift register (`1'). 2. The last bit is clocked into the first shift register (`1'). 3. A transition on the REGIN signal generates an internal load pulse that loads the control word into the parallel register. The circuit enters the new mode (in this case Tx-mode). The circuit stabilizes in the new mode. 4. When the clock signal goes low, the power amplifier (PA) is turned on slowly in order to minimize spurious components on the RF output signal. To be sure the PLL is in lock before the PA is turned on, the PA should be turned on after LOCKDET has been set. The negative transition on the clock signal should come a minimum time of one period of the comparison frequency after the internal load pulse is generated. 5. The power amplifier is fully turned on. Tx Rx 0 0 Binary form: (MSB to the left): Tx: 001001 011011 000010001001 000010000110 0001100101 0001100011 011110000000001010001011 Rx: 110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000001010001001 When FSK modulation is implemented by switching between the different dividers A, N and M values corresponding to the receive frequency and both transmit frequencies have to be found. MICRF500 16 March 2003 MICRF500 Example 2. fRF = 869.0MHz, fRF = 10.00MHz. FSK modulation is applied to the VCO. A1 Tx Rx 50 50 RxFilt Tx Rx 0 0 Ref6 Tx Rx 0 0 Ref0 Tx Rx 0 0 OutS1 Tx Rx 0 0 A0 50 50 Pa2 1 1 Ref5 0 0 N1 135 135 Pa1 1 1 Ref4 0 0 N0 135 135 Pa0 1 1 Ref3 0 0 Fc1 1 1 Mod0 0 0 M1 100 100 Gc 1 1 Ref2 0 0 Fc0 0 0 RT 1 0 M0 100 100 ByLNA 0 0 Ref1 0 0 OutS2 0 0 Pu 1 1 Micrel Binary form: (MSB to the left): Tx: 110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000010100000011 Rx: 111011 111011 000010001110 000010001110 0001101010 0001101010 01011110000000010100000001 With modulation applied to the VCO, A, N and M values corresponding to the receive frequency have to be found. The same set of A, N and M values are used in all modes. Programming After Battery Reset In order to ensure a successful programming after VDD has been zero volts, the PDEXT needs to be kept low during the first programming sequence. This can be done by a separate 110-line from a microcontroller, or a RC circuit on the PDEXT pin to VDD (A capcitor between PDEXT and VDD). Using the latter method, R and C values need to be chosen so that the voltage on the PDEXT pin is lower than VDD/2 when the controller word is loaded into the parallel register (see Figure 10). Cpmp1 Cpmp0 0 0 OutS0 0 0 1 1 Mod1 0 0 March 2003 17 MICRF500 MICRF500 Micrel Package Information 0.5510.012 (14.00.3) 0.3940.012 (10.00.3) 0.3150.012 (8.00.3) 44 34 1 0.031 (0.8) 33 11 23 12 0.039 (1.0) 22 0.0850.004 (2.150.1) 0.002 (0.05) 0.016 (0.4) 0.047 (1.2) 44-Pin LQFP (BLQ) MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA FAX + 1 (408) 944-0800 + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated. MICRF500 18 March 2003 |
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